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Internship - Verification Infrastructure | Infineon Careers

Job Description
In your new role you will:

• Receive training and improve your verification, SystemVerilog, UVM and formal verification knowledge
• Work in a team providing verification components with high re-usability
• Work on verification methodologies for both simulation and formal including power aware verification topics
• Debug and root cause issues with simulations including inside Testbench environments
• Have support from a team and supervisor to help you efficiently ramp up and work in the team

Your Profile
You are best equipped for this task if you have:

• Student of Electronics or equivalent major
• Knowledge of electronic devices and circuits, digital integrated circuits, computer architecture
• Knowledge of hardware description language (Verilog/VDHL), hardware (functional) simulation
• Basic knowledge about Object-Oriented Programming
• Able to read English documents

Nice-to-have:

• Knowledge or experience on hardware verification language (SystemVerilog) and methodology (UVM)
• Hands-on experience with hardware simulation tools and scripting
• Experience with working on Unix/Linux environment
• Hands-on experience with FPGA
• Experience working in university labs on IC design topics